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Merge 99665932d1 into fc6d3defde
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commit
bc254dbdd1
1 changed files with 2 additions and 2 deletions
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@ -938,7 +938,7 @@ class MiddlewareActor(
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private def inSubslotNotMissing(slot: Int, subslot: Int, inner: ByteVector): Unit = {
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if (subslot == inSubslot + 1) {
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in(PacketCoding.decodePacket(inner))
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send(RelatedB(slot, subslot))
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send(RelatedB(slot % 4, subslot))
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inSubslot = subslot
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} else if (subslot > inSubslot + 1) {
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in(PacketCoding.decodePacket(inner))
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@ -1011,7 +1011,7 @@ class MiddlewareActor(
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if (inSubslotsMissing.isEmpty) {
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subslotMissingProcessor.cancel()
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activeSubslotsFunc = inSubslotNotMissing
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send(RelatedB(slot, inSubslot)) //send a confirmation packet after all requested packets are handled
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send(RelatedB(slot % 4, inSubslot)) //send a confirmation packet after all requested packets are handled
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log.trace("normalcy with packet subslot order; resuming normal workflow")
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}
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}
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