mirror of
https://github.com/TorqueGameEngines/Torque3D.git
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120 lines
3.9 KiB
C++
120 lines
3.9 KiB
C++
// Original code is:
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// Copyright (c) 2005 Intel Corporation
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// All Rights Reserved
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//
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// CPUCount.cpp : Detects three forms of hardware multi-threading support across IA-32 platform
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// The three forms of HW multithreading are: Multi-processor, Multi-core, and
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// HyperThreading Technology.
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// This application enumerates all the logical processors enabled by OS and BIOS,
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// determine the HW topology of these enabled logical processors in the system
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// using information provided by CPUID instruction.
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// A multi-processing system can support any combination of the three forms of HW
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// multi-threading support. The relevant topology can be identified using a
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// three level decomposition of the "initial APIC ID" into
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// Package_id, core_id, and SMT_id. Such decomposition provides a three-level map of
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// the topology of hardware resources and
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// allow multi-threaded software to manage shared hardware resources in
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// the platform to reduce resource contention
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// Multicore detection algorithm for processor and cache topology requires
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// all leaf functions of CPUID instructions be available. System administrator
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// must ensure BIOS settings is not configured to restrict CPUID functionalities.
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//-------------------------------------------------------------------------------------------------
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#include "platform/platform.h"
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#if defined( TORQUE_OS_WIN )
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#include "platform/platformCPUCount.h"
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#include <windows.h>
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#include <intrin.h>
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#include <stdio.h>
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#include <assert.h>
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namespace CPUInfo {
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// based on http://msdn.microsoft.com/en-us/library/ms683194.aspx
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// Helper function to count set bits in the processor mask.
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DWORD CountSetBits( ULONG_PTR bitMask )
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{
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DWORD LSHIFT = sizeof( ULONG_PTR ) * 8 - 1;
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DWORD bitSetCount = 0;
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ULONG_PTR bitTest = (ULONG_PTR)1 << LSHIFT;
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DWORD i;
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for( i = 0; i <= LSHIFT; ++i )
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{
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bitSetCount += ((bitMask & bitTest) ? 1 : 0);
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bitTest /= 2;
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}
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return bitSetCount;
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}
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EConfig CPUCount( U32& TotAvailLogical, U32& TotAvailCore, U32& PhysicalNum )
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{
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EConfig StatusFlag = CONFIG_UserConfigIssue;
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TotAvailLogical = 0;
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TotAvailCore = 0;
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PhysicalNum = 0;
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PSYSTEM_LOGICAL_PROCESSOR_INFORMATION buffer = NULL;
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DWORD returnLength = 0;
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// get buffer length
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DWORD rc = GetLogicalProcessorInformation( buffer, &returnLength );
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buffer = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION)malloc( returnLength );
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rc = GetLogicalProcessorInformation( buffer, &returnLength );
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if( FALSE == rc )
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{
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free( buffer );
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return StatusFlag;
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}
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PSYSTEM_LOGICAL_PROCESSOR_INFORMATION ptr = buffer;
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DWORD byteOffset = 0;
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while( byteOffset + sizeof( SYSTEM_LOGICAL_PROCESSOR_INFORMATION ) <= returnLength )
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{
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switch( ptr->Relationship )
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{
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case RelationProcessorCore:
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TotAvailCore++;
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// A hyperthreaded core supplies more than one logical processor.
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TotAvailLogical += CountSetBits( ptr->ProcessorMask );
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break;
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case RelationProcessorPackage:
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// Logical processors share a physical package.
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PhysicalNum++;
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break;
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default:
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break;
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}
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byteOffset += sizeof( SYSTEM_LOGICAL_PROCESSOR_INFORMATION );
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ptr++;
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}
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free( buffer );
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StatusFlag = CONFIG_SingleCoreAndHTNotCapable;
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if( TotAvailCore == 1 && TotAvailLogical > TotAvailCore )
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StatusFlag = CONFIG_SingleCoreHTEnabled;
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else if( TotAvailCore > 1 && TotAvailLogical == TotAvailCore )
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StatusFlag = CONFIG_MultiCoreAndHTNotCapable;
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else if( TotAvailCore > 1 && TotAvailLogical > TotAvailCore )
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StatusFlag = CONFIG_MultiCoreAndHTEnabled;
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return StatusFlag;
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}
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} // namespace CPUInfo
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#endif
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