mirror of
https://github.com/TorqueGameEngines/Torque3D.git
synced 2026-02-20 15:13:45 +00:00
Merge branch 'Preview4_0' into feature-vfs-security
This commit is contained in:
Robert MacGregor
commit
161ffc62fe
3013 changed files with 348715 additions and 182470 deletions
|
|
@ -55,50 +55,11 @@
|
|||
/// @note These enums must be globally scoped so that they work with the inline assembly
|
||||
enum ProcessorType
|
||||
{
|
||||
// x86
|
||||
CPU_X86Compatible,
|
||||
CPU_Intel_Unknown,
|
||||
CPU_Intel_486,
|
||||
CPU_Intel_Pentium,
|
||||
CPU_Intel_PentiumMMX,
|
||||
CPU_Intel_PentiumPro,
|
||||
CPU_Intel_PentiumII,
|
||||
CPU_Intel_PentiumCeleron,
|
||||
CPU_Intel_PentiumIII,
|
||||
CPU_Intel_Pentium4,
|
||||
CPU_Intel_PentiumM,
|
||||
CPU_Intel_Core,
|
||||
CPU_Intel_Core2,
|
||||
CPU_Intel_Corei7Xeon, // Core i7 or Xeon
|
||||
CPU_AMD_K6,
|
||||
CPU_AMD_K6_2,
|
||||
CPU_AMD_K6_3,
|
||||
CPU_AMD_Athlon,
|
||||
CPU_AMD_Phenom,
|
||||
CPU_AMD_PhenomII,
|
||||
CPU_AMD_Bulldozer,
|
||||
CPU_AMD_Unknown,
|
||||
CPU_Cyrix_6x86,
|
||||
CPU_Cyrix_MediaGX,
|
||||
CPU_Cyrix_6x86MX,
|
||||
CPU_Cyrix_GXm, ///< Media GX w/ MMX
|
||||
CPU_Cyrix_Unknown,
|
||||
|
||||
// PowerPC
|
||||
CPU_PowerPC_Unknown,
|
||||
CPU_PowerPC_601,
|
||||
CPU_PowerPC_603,
|
||||
CPU_PowerPC_603e,
|
||||
CPU_PowerPC_603ev,
|
||||
CPU_PowerPC_604,
|
||||
CPU_PowerPC_604e,
|
||||
CPU_PowerPC_604ev,
|
||||
CPU_PowerPC_G3,
|
||||
CPU_PowerPC_G4,
|
||||
CPU_PowerPC_G4_7450,
|
||||
CPU_PowerPC_G4_7455,
|
||||
CPU_PowerPC_G4_7447,
|
||||
CPU_PowerPC_G5,
|
||||
CPU_ArmCompatible,
|
||||
CPU_Intel,
|
||||
CPU_AMD,
|
||||
CPU_Apple
|
||||
};
|
||||
|
||||
/// Properties for CPU.
|
||||
|
|
@ -107,17 +68,17 @@ enum ProcessorProperties
|
|||
CPU_PROP_C = (1<<0), ///< We should use C fallback math functions.
|
||||
CPU_PROP_FPU = (1<<1), ///< Has an FPU. (It better!)
|
||||
CPU_PROP_MMX = (1<<2), ///< Supports MMX instruction set extension.
|
||||
CPU_PROP_3DNOW = (1<<3), ///< Supports AMD 3dNow! instruction set extension.
|
||||
CPU_PROP_SSE = (1<<4), ///< Supports SSE instruction set extension.
|
||||
CPU_PROP_RDTSC = (1<<5), ///< Supports Read Time Stamp Counter op.
|
||||
CPU_PROP_SSE2 = (1<<6), ///< Supports SSE2 instruction set extension.
|
||||
CPU_PROP_SSE3 = (1<<7), ///< Supports SSE3 instruction set extension.
|
||||
CPU_PROP_SSE3xt = (1<<8), ///< Supports extended SSE3 instruction set
|
||||
CPU_PROP_SSE4_1 = (1<<9), ///< Supports SSE4_1 instruction set extension.
|
||||
CPU_PROP_SSE4_2 = (1<<10), ///< Supports SSE4_2 instruction set extension.
|
||||
CPU_PROP_MP = (1<<11), ///< This is a multi-processor system.
|
||||
CPU_PROP_LE = (1<<12), ///< This processor is LITTLE ENDIAN.
|
||||
CPU_PROP_64bit = (1<<13), ///< This processor is 64-bit capable
|
||||
CPU_PROP_SSE = (1<<3), ///< Supports SSE instruction set extension.
|
||||
CPU_PROP_SSE2 = (1<<4), ///< Supports SSE2 instruction set extension.
|
||||
CPU_PROP_SSE3 = (1<<5), ///< Supports SSE3 instruction set extension.
|
||||
CPU_PROP_SSE3ex = (1<<6), ///< Supports Supplemental SSE3 instruction set
|
||||
CPU_PROP_SSE4_1 = (1<<7), ///< Supports SSE4_1 instruction set extension.
|
||||
CPU_PROP_SSE4_2 = (1<<8), ///< Supports SSE4_2 instruction set extension.
|
||||
CPU_PROP_AVX = (1<<9), ///< Supports AVX256 instruction set extension.
|
||||
CPU_PROP_MP = (1<<10), ///< This is a multi-processor system.
|
||||
CPU_PROP_LE = (1<<11), ///< This processor is LITTLE ENDIAN.
|
||||
CPU_PROP_64bit = (1<<12), ///< This processor is 64-bit capable
|
||||
CPU_PROP_NEON = (1<<13), ///< Supports the Arm Neon instruction set extension.
|
||||
};
|
||||
|
||||
/// Processor info manager.
|
||||
|
|
@ -336,7 +297,6 @@ namespace Platform
|
|||
bool isHyperThreaded;
|
||||
U32 numLogicalProcessors;
|
||||
U32 numPhysicalProcessors;
|
||||
U32 numAvailableCores;
|
||||
U32 properties; // CPU type specific enum
|
||||
} processor;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -28,264 +28,47 @@
|
|||
|
||||
Signal<void(void)> Platform::SystemInfoReady;
|
||||
|
||||
enum CPUFlags
|
||||
{
|
||||
// EDX Register flags
|
||||
BIT_FPU = BIT(0),
|
||||
BIT_RDTSC = BIT(4),
|
||||
BIT_MMX = BIT(23),
|
||||
BIT_SSE = BIT(25),
|
||||
BIT_SSE2 = BIT(26),
|
||||
BIT_3DNOW = BIT(31),
|
||||
|
||||
// These use a different value for comparison than the above flags (ECX Register)
|
||||
BIT_SSE3 = BIT(0),
|
||||
BIT_SSE3xt = BIT(9),
|
||||
BIT_SSE4_1 = BIT(19),
|
||||
BIT_SSE4_2 = BIT(20),
|
||||
};
|
||||
|
||||
// fill the specified structure with information obtained from asm code
|
||||
void SetProcessorInfo(Platform::SystemInfo_struct::Processor& pInfo,
|
||||
char* vendor, U32 processor, U32 properties, U32 properties2)
|
||||
void SetProcessorInfo(Platform::SystemInfo_struct::Processor& pInfo, const char* vendor, const char* brand)
|
||||
{
|
||||
Platform::SystemInfo.processor.properties |= (properties & BIT_FPU) ? CPU_PROP_FPU : 0;
|
||||
Platform::SystemInfo.processor.properties |= (properties & BIT_RDTSC) ? CPU_PROP_RDTSC : 0;
|
||||
Platform::SystemInfo.processor.properties |= (properties & BIT_MMX) ? CPU_PROP_MMX : 0;
|
||||
|
||||
if (dStricmp(vendor, "GenuineIntel") == 0)
|
||||
{
|
||||
pInfo.properties |= (properties & BIT_SSE) ? CPU_PROP_SSE : 0;
|
||||
pInfo.properties |= (properties & BIT_SSE2) ? CPU_PROP_SSE2 : 0;
|
||||
pInfo.properties |= (properties2 & BIT_SSE3) ? CPU_PROP_SSE3 : 0;
|
||||
pInfo.properties |= (properties2 & BIT_SSE3xt) ? CPU_PROP_SSE3xt : 0;
|
||||
pInfo.properties |= (properties2 & BIT_SSE4_1) ? CPU_PROP_SSE4_1 : 0;
|
||||
pInfo.properties |= (properties2 & BIT_SSE4_2) ? CPU_PROP_SSE4_2 : 0;
|
||||
|
||||
pInfo.type = CPU_Intel_Unknown;
|
||||
// switch on processor family code
|
||||
switch ((processor >> 8) & 0x0f)
|
||||
{
|
||||
case 4:
|
||||
pInfo.type = CPU_Intel_486;
|
||||
pInfo.name = StringTable->insert("Intel 486 class");
|
||||
break;
|
||||
|
||||
// Pentium Family
|
||||
case 5:
|
||||
// switch on processor model code
|
||||
switch ((processor >> 4) & 0xf)
|
||||
{
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
pInfo.type = CPU_Intel_Pentium;
|
||||
pInfo.name = StringTable->insert("Intel Pentium");
|
||||
break;
|
||||
case 4:
|
||||
pInfo.type = CPU_Intel_PentiumMMX;
|
||||
pInfo.name = StringTable->insert("Intel Pentium MMX");
|
||||
break;
|
||||
default:
|
||||
pInfo.type = CPU_Intel_Pentium;
|
||||
pInfo.name = StringTable->insert( "Intel (unknown)" );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
// Pentium Pro/II/II family
|
||||
case 6:
|
||||
{
|
||||
U32 extendedModel = ( processor & 0xf0000 ) >> 16;
|
||||
// switch on processor model code
|
||||
switch ((processor >> 4) & 0xf)
|
||||
{
|
||||
case 1:
|
||||
pInfo.type = CPU_Intel_PentiumPro;
|
||||
pInfo.name = StringTable->insert("Intel Pentium Pro");
|
||||
break;
|
||||
case 3:
|
||||
case 5:
|
||||
pInfo.type = CPU_Intel_PentiumII;
|
||||
pInfo.name = StringTable->insert("Intel Pentium II");
|
||||
break;
|
||||
case 6:
|
||||
pInfo.type = CPU_Intel_PentiumCeleron;
|
||||
pInfo.name = StringTable->insert("Intel Pentium Celeron");
|
||||
break;
|
||||
case 7:
|
||||
case 8:
|
||||
case 11:
|
||||
pInfo.type = CPU_Intel_PentiumIII;
|
||||
pInfo.name = StringTable->insert("Intel Pentium III");
|
||||
break;
|
||||
case 0xA:
|
||||
if( extendedModel == 1)
|
||||
{
|
||||
pInfo.type = CPU_Intel_Corei7Xeon;
|
||||
pInfo.name = StringTable->insert( "Intel Core i7 / Xeon" );
|
||||
}
|
||||
else
|
||||
{
|
||||
pInfo.type = CPU_Intel_PentiumIII;
|
||||
pInfo.name = StringTable->insert( "Intel Pentium III Xeon" );
|
||||
}
|
||||
break;
|
||||
case 0xD:
|
||||
if( extendedModel == 1 )
|
||||
{
|
||||
pInfo.type = CPU_Intel_Corei7Xeon;
|
||||
pInfo.name = StringTable->insert( "Intel Core i7 / Xeon" );
|
||||
}
|
||||
else
|
||||
{
|
||||
pInfo.type = CPU_Intel_PentiumM;
|
||||
pInfo.name = StringTable->insert( "Intel Pentium/Celeron M" );
|
||||
}
|
||||
break;
|
||||
case 0xE:
|
||||
pInfo.type = CPU_Intel_Core;
|
||||
pInfo.name = StringTable->insert( "Intel Core" );
|
||||
break;
|
||||
case 0xF:
|
||||
pInfo.type = CPU_Intel_Core2;
|
||||
pInfo.name = StringTable->insert( "Intel Core 2" );
|
||||
break;
|
||||
default:
|
||||
pInfo.type = CPU_Intel_PentiumPro;
|
||||
pInfo.name = StringTable->insert( "Intel (unknown)" );
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// Pentium4 Family
|
||||
case 0xf:
|
||||
pInfo.type = CPU_Intel_Pentium4;
|
||||
pInfo.name = StringTable->insert( "Intel Pentium 4" );
|
||||
break;
|
||||
|
||||
default:
|
||||
pInfo.type = CPU_Intel_Unknown;
|
||||
pInfo.name = StringTable->insert( "Intel (unknown)" );
|
||||
break;
|
||||
}
|
||||
pInfo.type = CPU_Intel;
|
||||
pInfo.name = StringTable->insert(brand ? brand : "Intel (Unknown)");
|
||||
}
|
||||
//--------------------------------------
|
||||
else if (dStricmp(vendor, "AuthenticAMD") == 0)
|
||||
{
|
||||
pInfo.name = StringTable->insert(brand ? brand : "AMD (unknown)");
|
||||
pInfo.type = CPU_AMD;
|
||||
}
|
||||
else if (dStricmp(vendor, "Apple") == 0)
|
||||
{
|
||||
pInfo.name = StringTable->insert(brand ? brand : "Apple (unknown)");
|
||||
pInfo.type = CPU_Apple;
|
||||
}
|
||||
else
|
||||
if (dStricmp(vendor, "AuthenticAMD") == 0)
|
||||
{
|
||||
// AthlonXP processors support SSE
|
||||
pInfo.properties |= (properties & BIT_SSE) ? CPU_PROP_SSE : 0;
|
||||
pInfo.properties |= ( properties & BIT_SSE2 ) ? CPU_PROP_SSE2 : 0;
|
||||
pInfo.properties |= (properties & BIT_3DNOW) ? CPU_PROP_3DNOW : 0;
|
||||
// Phenom and PhenomII support SSE3, SSE4a
|
||||
pInfo.properties |= ( properties2 & BIT_SSE3 ) ? CPU_PROP_SSE3 : 0;
|
||||
pInfo.properties |= ( properties2 & BIT_SSE4_1 ) ? CPU_PROP_SSE4_1 : 0;
|
||||
// switch on processor family code
|
||||
switch ((processor >> 8) & 0xf)
|
||||
{
|
||||
// K6 Family
|
||||
case 5:
|
||||
// switch on processor model code
|
||||
switch ((processor >> 4) & 0xf)
|
||||
{
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
pInfo.type = CPU_AMD_K6_3;
|
||||
pInfo.name = StringTable->insert("AMD K5");
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
pInfo.type = CPU_AMD_K6;
|
||||
pInfo.name = StringTable->insert("AMD K6");
|
||||
break;
|
||||
case 8:
|
||||
pInfo.type = CPU_AMD_K6_2;
|
||||
pInfo.name = StringTable->insert("AMD K6-2");
|
||||
break;
|
||||
case 9:
|
||||
case 10:
|
||||
case 11:
|
||||
case 12:
|
||||
case 13:
|
||||
case 14:
|
||||
case 15:
|
||||
pInfo.type = CPU_AMD_K6_3;
|
||||
pInfo.name = StringTable->insert("AMD K6-3");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
// Athlon Family
|
||||
case 6:
|
||||
pInfo.type = CPU_AMD_Athlon;
|
||||
pInfo.name = StringTable->insert("AMD Athlon");
|
||||
break;
|
||||
|
||||
// Phenom Family
|
||||
case 15:
|
||||
pInfo.type = CPU_AMD_Phenom;
|
||||
pInfo.name = StringTable->insert("AMD Phenom");
|
||||
break;
|
||||
|
||||
// Phenom II Family
|
||||
case 16:
|
||||
pInfo.type = CPU_AMD_PhenomII;
|
||||
pInfo.name = StringTable->insert("AMD Phenom II");
|
||||
break;
|
||||
|
||||
// Bulldozer Family
|
||||
case 17:
|
||||
pInfo.type = CPU_AMD_Bulldozer;
|
||||
pInfo.name = StringTable->insert("AMD Bulldozer");
|
||||
break;
|
||||
|
||||
default:
|
||||
pInfo.type = CPU_AMD_Unknown;
|
||||
pInfo.name = StringTable->insert("AMD (unknown)");
|
||||
break;
|
||||
}
|
||||
}
|
||||
//--------------------------------------
|
||||
else
|
||||
if (dStricmp(vendor, "CyrixInstead") == 0)
|
||||
{
|
||||
switch (processor)
|
||||
{
|
||||
case 0x520:
|
||||
pInfo.type = CPU_Cyrix_6x86;
|
||||
pInfo.name = StringTable->insert("Cyrix 6x86");
|
||||
break;
|
||||
case 0x440:
|
||||
pInfo.type = CPU_Cyrix_MediaGX;
|
||||
pInfo.name = StringTable->insert("Cyrix Media GX");
|
||||
break;
|
||||
case 0x600:
|
||||
pInfo.type = CPU_Cyrix_6x86MX;
|
||||
pInfo.name = StringTable->insert("Cyrix 6x86mx/MII");
|
||||
break;
|
||||
case 0x540:
|
||||
pInfo.type = CPU_Cyrix_GXm;
|
||||
pInfo.name = StringTable->insert("Cyrix GXm");
|
||||
break;
|
||||
default:
|
||||
pInfo.type = CPU_Cyrix_Unknown;
|
||||
pInfo.name = StringTable->insert("Cyrix (unknown)");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
{
|
||||
#if defined(TORQUE_CPU_X86) || defined(TORQUE_CPU_X64)
|
||||
|
||||
pInfo.name = StringTable->insert(brand ? brand : "x86 Compatible (unknown)");
|
||||
pInfo.type = CPU_X86Compatible;
|
||||
|
||||
#elif defined(TORQUE_CPU_ARM64)
|
||||
pInfo.name = StringTable->insert(brand ? brand : "Arm Compatible (unknown)");
|
||||
pInfo.type = CPU_ArmCompatible;
|
||||
|
||||
#else
|
||||
#error "Unknown CPU Architecture"
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
// Get multithreading caps.
|
||||
|
||||
CPUInfo::EConfig config = CPUInfo::CPUCount( pInfo.numLogicalProcessors, pInfo.numAvailableCores, pInfo.numPhysicalProcessors );
|
||||
CPUInfo::EConfig config = CPUInfo::CPUCount( pInfo.numLogicalProcessors, pInfo.numPhysicalProcessors );
|
||||
pInfo.isHyperThreaded = CPUInfo::isHyperThreaded( config );
|
||||
pInfo.isMultiCore = CPUInfo::isMultiCore( config );
|
||||
|
||||
// Trigger the signal
|
||||
Platform::SystemInfoReady.trigger();
|
||||
}
|
||||
}
|
||||
|
|
@ -1,657 +0,0 @@
|
|||
// Original code is:
|
||||
// Copyright (c) 2005 Intel Corporation
|
||||
// All Rights Reserved
|
||||
//
|
||||
// CPUCount.cpp : Detects three forms of hardware multi-threading support across IA-32 platform
|
||||
// The three forms of HW multithreading are: Multi-processor, Multi-core, and
|
||||
// HyperThreading Technology.
|
||||
// This application enumerates all the logical processors enabled by OS and BIOS,
|
||||
// determine the HW topology of these enabled logical processors in the system
|
||||
// using information provided by CPUID instruction.
|
||||
// A multi-processing system can support any combination of the three forms of HW
|
||||
// multi-threading support. The relevant topology can be identified using a
|
||||
// three level decomposition of the "initial APIC ID" into
|
||||
// Package_id, core_id, and SMT_id. Such decomposition provides a three-level map of
|
||||
// the topology of hardware resources and
|
||||
// allow multi-threaded software to manage shared hardware resources in
|
||||
// the platform to reduce resource contention
|
||||
|
||||
// Multicore detection algorithm for processor and cache topology requires
|
||||
// all leaf functions of CPUID instructions be available. System administrator
|
||||
// must ensure BIOS settings is not configured to restrict CPUID functionalities.
|
||||
//-------------------------------------------------------------------------------------------------
|
||||
|
||||
#if defined(TORQUE_OS_LINUX) || defined(LINUX)
|
||||
|
||||
// TODO GCC code don't compile on Release with optimizations, mover code to platform layer
|
||||
|
||||
#else
|
||||
|
||||
#include "platform/platform.h"
|
||||
#include "platform/platformCPUCount.h"
|
||||
|
||||
#if defined(TORQUE_OS_LINUX) || defined(TORQUE_OS_OSX)
|
||||
|
||||
#ifdef TORQUE_OS_LINUX
|
||||
// The Linux source code listing can be compiled using Linux kernel verison 2.6
|
||||
// or higher (e.g. RH 4AS-2.8 using GCC 3.4.4).
|
||||
// Due to syntax variances of Linux affinity APIs with earlier kernel versions
|
||||
// and dependence on glibc library versions, compilation on Linux environment
|
||||
// with older kernels and compilers may require kernel patches or compiler upgrades.
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
#include <string.h>
|
||||
#include <sched.h>
|
||||
#define DWORD unsigned long
|
||||
#elif defined( TORQUE_OS_WIN )
|
||||
#include <windows.h>
|
||||
#elif defined( TORQUE_OS_MAC )
|
||||
# include <sys/types.h>
|
||||
# include <sys/sysctl.h>
|
||||
#else
|
||||
#error Not implemented on platform.
|
||||
#endif
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
|
||||
namespace CPUInfo {
|
||||
|
||||
#define HWD_MT_BIT 0x10000000 // EDX[28] Bit 28 is set if HT or multi-core is supported
|
||||
#define NUM_LOGICAL_BITS 0x00FF0000 // EBX[23:16] Bit 16-23 in ebx contains the number of logical
|
||||
// processors per physical processor when execute cpuid with
|
||||
// eax set to 1
|
||||
#define NUM_CORE_BITS 0xFC000000 // EAX[31:26] Bit 26-31 in eax contains the number of cores minus one
|
||||
// per physical processor when execute cpuid with
|
||||
// eax set to 4.
|
||||
|
||||
|
||||
#define INITIAL_APIC_ID_BITS 0xFF000000 // EBX[31:24] Bits 24-31 (8 bits) return the 8-bit unique
|
||||
// initial APIC ID for the processor this code is running on.
|
||||
|
||||
|
||||
#ifndef TORQUE_OS_MAC
|
||||
static U32 CpuIDSupported(void);
|
||||
static U32 find_maskwidth(unsigned int);
|
||||
static U32 HWD_MTSupported(void);
|
||||
static U32 MaxLogicalProcPerPhysicalProc(void);
|
||||
static U32 MaxCorePerPhysicalProc(void);
|
||||
static U8 GetAPIC_ID(void);
|
||||
static U8 GetNzbSubID(U8, U8, U8);
|
||||
#endif
|
||||
|
||||
static char g_s3Levels[2048];
|
||||
|
||||
#ifndef TORQUE_OS_MAC
|
||||
|
||||
//
|
||||
// CpuIDSupported will return 0 if CPUID instruction is unavailable. Otherwise, it will return
|
||||
// the maximum supported standard function.
|
||||
//
|
||||
static U32 CpuIDSupported(void)
|
||||
{
|
||||
U32 maxInputValue = 0;
|
||||
// If CPUID instruction is supported
|
||||
#ifdef TORQUE_COMPILER_GCC
|
||||
try
|
||||
{
|
||||
// call cpuid with eax = 0
|
||||
asm
|
||||
(
|
||||
"pushl %%ebx\n\t"
|
||||
"xorl %%eax,%%eax\n\t"
|
||||
"cpuid\n\t"
|
||||
"popl %%ebx\n\t"
|
||||
: "=a" (maxInputValue)
|
||||
:
|
||||
: "%ecx", "%edx"
|
||||
);
|
||||
}
|
||||
catch (...)
|
||||
{
|
||||
return(0); // cpuid instruction is unavailable
|
||||
}
|
||||
#elif defined( TORQUE_COMPILER_VISUALC )
|
||||
try
|
||||
{
|
||||
// call cpuid with eax = 0
|
||||
__asm
|
||||
{
|
||||
xor eax, eax
|
||||
cpuid
|
||||
mov maxInputValue, eax
|
||||
}
|
||||
}
|
||||
catch (...)
|
||||
{
|
||||
// cpuid instruction is unavailable
|
||||
}
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
|
||||
return maxInputValue;
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Function returns the maximum cores per physical package. Note that the number of
|
||||
// AVAILABLE cores per physical to be used by an application might be less than this
|
||||
// maximum value.
|
||||
//
|
||||
|
||||
static U32 MaxCorePerPhysicalProc(void)
|
||||
{
|
||||
|
||||
U32 Regeax = 0;
|
||||
|
||||
if (!HWD_MTSupported()) return (U32) 1; // Single core
|
||||
#ifdef TORQUE_COMPILER_GCC
|
||||
{
|
||||
asm
|
||||
(
|
||||
"pushl %ebx\n\t"
|
||||
"xorl %eax, %eax\n\t"
|
||||
"cpuid\n\t"
|
||||
"cmpl $4, %eax\n\t" // check if cpuid supports leaf 4
|
||||
"jl .single_core\n\t" // Single core
|
||||
"movl $4, %eax\n\t"
|
||||
"movl $0, %ecx\n\t" // start with index = 0; Leaf 4 reports
|
||||
"popl %ebx\n\t"
|
||||
); // at least one valid cache level
|
||||
asm
|
||||
(
|
||||
"cpuid"
|
||||
: "=a" (Regeax)
|
||||
:
|
||||
: "%ecx", "%edx"
|
||||
);
|
||||
asm
|
||||
(
|
||||
"jmp .multi_core\n"
|
||||
".single_core:\n\t"
|
||||
"xor %eax, %eax\n"
|
||||
".multi_core:"
|
||||
);
|
||||
}
|
||||
#elif defined( TORQUE_COMPILER_VISUALC )
|
||||
__asm
|
||||
{
|
||||
xor eax, eax
|
||||
cpuid
|
||||
cmp eax, 4 // check if cpuid supports leaf 4
|
||||
jl single_core // Single core
|
||||
mov eax, 4
|
||||
mov ecx, 0 // start with index = 0; Leaf 4 reports
|
||||
cpuid // at least one valid cache level
|
||||
mov Regeax, eax
|
||||
jmp multi_core
|
||||
|
||||
single_core:
|
||||
xor eax, eax
|
||||
|
||||
multi_core:
|
||||
|
||||
}
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
return (U32)((Regeax & NUM_CORE_BITS) >> 26)+1;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// The function returns 0 when the hardware multi-threaded bit is not set.
|
||||
//
|
||||
static U32 HWD_MTSupported(void)
|
||||
{
|
||||
|
||||
|
||||
U32 Regedx = 0;
|
||||
|
||||
|
||||
if ((CpuIDSupported() >= 1))
|
||||
{
|
||||
#ifdef TORQUE_COMPILER_GCC
|
||||
asm
|
||||
(
|
||||
"pushl %%ebx\n\t"
|
||||
"movl $1,%%eax\n\t"
|
||||
"cpuid\n\t"
|
||||
"popl %%ebx\n\t"
|
||||
: "=d" (Regedx)
|
||||
:
|
||||
: "%eax","%ecx"
|
||||
);
|
||||
#elif defined( TORQUE_COMPILER_VISUALC )
|
||||
__asm
|
||||
{
|
||||
mov eax, 1
|
||||
cpuid
|
||||
mov Regedx, edx
|
||||
}
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
}
|
||||
|
||||
return (Regedx & HWD_MT_BIT);
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
//
|
||||
// Function returns the maximum logical processors per physical package. Note that the number of
|
||||
// AVAILABLE logical processors per physical to be used by an application might be less than this
|
||||
// maximum value.
|
||||
//
|
||||
static U32 MaxLogicalProcPerPhysicalProc(void)
|
||||
{
|
||||
|
||||
U32 Regebx = 0;
|
||||
|
||||
if (!HWD_MTSupported()) return (U32) 1;
|
||||
#ifdef TORQUE_COMPILER_GCC
|
||||
asm
|
||||
(
|
||||
"movl $1,%%eax\n\t"
|
||||
"cpuid"
|
||||
: "=b" (Regebx)
|
||||
:
|
||||
: "%eax","%ecx","%edx"
|
||||
);
|
||||
#elif defined( TORQUE_COMPILER_VISUALC )
|
||||
__asm
|
||||
{
|
||||
mov eax, 1
|
||||
cpuid
|
||||
mov Regebx, ebx
|
||||
}
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
return (unsigned int) ((Regebx & NUM_LOGICAL_BITS) >> 16);
|
||||
|
||||
}
|
||||
|
||||
|
||||
static U8 GetAPIC_ID(void)
|
||||
{
|
||||
|
||||
U32 Regebx = 0;
|
||||
#ifdef TORQUE_COMPILER_GCC
|
||||
asm
|
||||
(
|
||||
"movl $1, %%eax\n\t"
|
||||
"cpuid"
|
||||
: "=b" (Regebx)
|
||||
:
|
||||
: "%eax","%ecx","%edx"
|
||||
);
|
||||
|
||||
#elif defined( TORQUE_COMPILER_VISUALC )
|
||||
__asm
|
||||
{
|
||||
mov eax, 1
|
||||
cpuid
|
||||
mov Regebx, ebx
|
||||
}
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
|
||||
return (unsigned char) ((Regebx & INITIAL_APIC_ID_BITS) >> 24);
|
||||
|
||||
}
|
||||
|
||||
//
|
||||
// Determine the width of the bit field that can represent the value count_item.
|
||||
//
|
||||
U32 find_maskwidth(U32 CountItem)
|
||||
{
|
||||
U32 MaskWidth,
|
||||
count = CountItem;
|
||||
#ifdef TORQUE_COMPILER_GCC
|
||||
asm
|
||||
(
|
||||
#ifdef __x86_64__ // define constant to compile
|
||||
"push %%rcx\n\t" // under 64-bit Linux
|
||||
"push %%rax\n\t"
|
||||
#else
|
||||
"pushl %%ecx\n\t"
|
||||
"pushl %%eax\n\t"
|
||||
#endif
|
||||
// "movl $count, %%eax\n\t" //done by Assembler below
|
||||
"xorl %%ecx, %%ecx"
|
||||
// "movl %%ecx, MaskWidth\n\t" //done by Assembler below
|
||||
: "=c" (MaskWidth)
|
||||
: "a" (count)
|
||||
// : "%ecx", "%eax" We don't list these as clobbered because we don't want the assembler
|
||||
//to put them back when we are done
|
||||
);
|
||||
asm
|
||||
(
|
||||
"decl %%eax\n\t"
|
||||
"bsrw %%ax,%%cx\n\t"
|
||||
"jz next\n\t"
|
||||
"incw %%cx\n\t"
|
||||
// "movl %%ecx, MaskWidth\n" //done by Assembler below
|
||||
: "=c" (MaskWidth)
|
||||
:
|
||||
);
|
||||
asm
|
||||
(
|
||||
"next:\n\t"
|
||||
#ifdef __x86_64__
|
||||
"pop %rax\n\t"
|
||||
"pop %rcx"
|
||||
#else
|
||||
"popl %eax\n\t"
|
||||
"popl %ecx"
|
||||
#endif
|
||||
);
|
||||
|
||||
#elif defined( TORQUE_COMPILER_VISUALC )
|
||||
__asm
|
||||
{
|
||||
mov eax, count
|
||||
mov ecx, 0
|
||||
mov MaskWidth, ecx
|
||||
dec eax
|
||||
bsr cx, ax
|
||||
jz next
|
||||
inc cx
|
||||
mov MaskWidth, ecx
|
||||
next:
|
||||
|
||||
}
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
return MaskWidth;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Extract the subset of bit field from the 8-bit value FullID. It returns the 8-bit sub ID value
|
||||
//
|
||||
static U8 GetNzbSubID(U8 FullID,
|
||||
U8 MaxSubIDValue,
|
||||
U8 ShiftCount)
|
||||
{
|
||||
U32 MaskWidth;
|
||||
U8 MaskBits;
|
||||
|
||||
MaskWidth = find_maskwidth((U32) MaxSubIDValue);
|
||||
MaskBits = (0xff << ShiftCount) ^
|
||||
((U8) (0xff << (ShiftCount + MaskWidth)));
|
||||
|
||||
return (FullID & MaskBits);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
//
|
||||
//
|
||||
//
|
||||
EConfig CPUCount(U32& TotAvailLogical, U32& TotAvailCore, U32& PhysicalNum)
|
||||
{
|
||||
EConfig StatusFlag = CONFIG_UserConfigIssue;
|
||||
|
||||
g_s3Levels[0] = 0;
|
||||
TotAvailCore = 1;
|
||||
PhysicalNum = 1;
|
||||
|
||||
U32 numLPEnabled = 0;
|
||||
S32 MaxLPPerCore = 1;
|
||||
|
||||
#ifdef TORQUE_OS_MAC
|
||||
|
||||
//FIXME: This isn't a proper port but more or less just some sneaky cheating
|
||||
// to get around having to mess with yet another crap UNIX-style API. Seems
|
||||
// like there isn't a way to do this that's working across all OSX incarnations
|
||||
// and machine configurations anyway.
|
||||
|
||||
S32 numCPUs;
|
||||
S32 numPackages;
|
||||
|
||||
// Get the number of CPUs.
|
||||
|
||||
size_t len = sizeof( numCPUs );
|
||||
if( sysctlbyname( "hw.ncpu", &numCPUs, &len, 0, 0 ) == -1 )
|
||||
return CONFIG_UserConfigIssue;
|
||||
|
||||
// Get the number of packages.
|
||||
len = sizeof( numPackages );
|
||||
if( sysctlbyname( "hw.packages", &numPackages, &len, 0, 0 ) == -1 )
|
||||
return CONFIG_UserConfigIssue;
|
||||
|
||||
TotAvailCore = numCPUs;
|
||||
TotAvailLogical = numCPUs;
|
||||
PhysicalNum = numPackages;
|
||||
#else
|
||||
|
||||
U32 dwAffinityMask;
|
||||
S32 j = 0;
|
||||
U8 apicID, PackageIDMask;
|
||||
U8 tblPkgID[256], tblCoreID[256], tblSMTID[256];
|
||||
char tmp[256];
|
||||
|
||||
#ifdef TORQUE_OS_LINUX
|
||||
//we need to make sure that this process is allowed to run on
|
||||
//all of the logical processors that the OS itself can run on.
|
||||
//A process could acquire/inherit affinity settings that restricts the
|
||||
// current process to run on a subset of all logical processor visible to OS.
|
||||
|
||||
// Linux doesn't easily allow us to look at the Affinity Bitmask directly,
|
||||
// but it does provide an API to test affinity maskbits of the current process
|
||||
// against each logical processor visible under OS.
|
||||
S32 sysNumProcs = sysconf(_SC_NPROCESSORS_CONF); //This will tell us how many
|
||||
//CPUs are currently enabled.
|
||||
|
||||
//this will tell us which processors this process can run on.
|
||||
cpu_set_t allowedCPUs;
|
||||
sched_getaffinity(0, sizeof(allowedCPUs), &allowedCPUs);
|
||||
|
||||
for (S32 i = 0; i < sysNumProcs; i++ )
|
||||
{
|
||||
if ( CPU_ISSET(i, &allowedCPUs) == 0 )
|
||||
return CONFIG_UserConfigIssue;
|
||||
}
|
||||
#elif defined( TORQUE_OS_WIN )
|
||||
DWORD dwProcessAffinity, dwSystemAffinity;
|
||||
GetProcessAffinityMask(GetCurrentProcess(),
|
||||
&dwProcessAffinity,
|
||||
&dwSystemAffinity);
|
||||
if (dwProcessAffinity != dwSystemAffinity) // not all CPUs are enabled
|
||||
return CONFIG_UserConfigIssue;
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
|
||||
// Assume that cores within a package have the SAME number of
|
||||
// logical processors. Also, values returned by
|
||||
// MaxLogicalProcPerPhysicalProc and MaxCorePerPhysicalProc do not have
|
||||
// to be power of 2.
|
||||
|
||||
MaxLPPerCore = MaxLogicalProcPerPhysicalProc() / MaxCorePerPhysicalProc();
|
||||
dwAffinityMask = 1;
|
||||
|
||||
#ifdef TORQUE_OS_LINUX
|
||||
cpu_set_t currentCPU;
|
||||
while ( j < sysNumProcs )
|
||||
{
|
||||
CPU_ZERO(¤tCPU);
|
||||
CPU_SET(j, ¤tCPU);
|
||||
if ( sched_setaffinity (0, sizeof(currentCPU), ¤tCPU) == 0 )
|
||||
{
|
||||
sleep(0); // Ensure system to switch to the right CPU
|
||||
#elif defined( TORQUE_OS_WIN )
|
||||
while (dwAffinityMask && dwAffinityMask <= dwSystemAffinity)
|
||||
{
|
||||
if (SetThreadAffinityMask(GetCurrentThread(), dwAffinityMask))
|
||||
{
|
||||
Sleep(0); // Ensure system to switch to the right CPU
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
apicID = GetAPIC_ID();
|
||||
|
||||
|
||||
// Store SMT ID and core ID of each logical processor
|
||||
// Shift vlaue for SMT ID is 0
|
||||
// Shift value for core ID is the mask width for maximum logical
|
||||
// processors per core
|
||||
|
||||
tblSMTID[j] = GetNzbSubID(apicID, MaxLPPerCore, 0);
|
||||
U8 maxCorePPP = MaxCorePerPhysicalProc();
|
||||
U8 maskWidth = find_maskwidth(MaxLPPerCore);
|
||||
tblCoreID[j] = GetNzbSubID(apicID, maxCorePPP, maskWidth);
|
||||
|
||||
// Extract package ID, assume single cluster.
|
||||
// Shift value is the mask width for max Logical per package
|
||||
|
||||
PackageIDMask = (unsigned char) (0xff <<
|
||||
find_maskwidth(MaxLogicalProcPerPhysicalProc()));
|
||||
|
||||
tblPkgID[j] = apicID & PackageIDMask;
|
||||
sprintf(tmp," AffinityMask = %d; Initial APIC = %d; Physical ID = %d, Core ID = %d, SMT ID = %d\n",
|
||||
dwAffinityMask, apicID, tblPkgID[j], tblCoreID[j], tblSMTID[j]);
|
||||
dStrcat(g_s3Levels, tmp, 2048);
|
||||
|
||||
numLPEnabled ++; // Number of available logical processors in the system.
|
||||
|
||||
} // if
|
||||
|
||||
j++;
|
||||
dwAffinityMask = 1 << j;
|
||||
} // while
|
||||
|
||||
// restore the affinity setting to its original state
|
||||
#ifdef TORQUE_OS_LINUX
|
||||
sched_setaffinity (0, sizeof(allowedCPUs), &allowedCPUs);
|
||||
sleep(0);
|
||||
#elif defined( TORQUE_OS_WIN )
|
||||
SetThreadAffinityMask(GetCurrentThread(), dwProcessAffinity);
|
||||
Sleep(0);
|
||||
#else
|
||||
# error Not implemented.
|
||||
#endif
|
||||
TotAvailLogical = numLPEnabled;
|
||||
|
||||
//
|
||||
// Count available cores (TotAvailCore) in the system
|
||||
//
|
||||
U8 CoreIDBucket[256];
|
||||
DWORD ProcessorMask, pCoreMask[256];
|
||||
U32 i, ProcessorNum;
|
||||
|
||||
CoreIDBucket[0] = tblPkgID[0] | tblCoreID[0];
|
||||
ProcessorMask = 1;
|
||||
pCoreMask[0] = ProcessorMask;
|
||||
|
||||
for (ProcessorNum = 1; ProcessorNum < numLPEnabled; ProcessorNum++)
|
||||
{
|
||||
ProcessorMask <<= 1;
|
||||
for (i = 0; i < TotAvailCore; i++)
|
||||
{
|
||||
// Comparing bit-fields of logical processors residing in different packages
|
||||
// Assuming the bit-masks are the same on all processors in the system.
|
||||
if ((tblPkgID[ProcessorNum] | tblCoreID[ProcessorNum]) == CoreIDBucket[i])
|
||||
{
|
||||
pCoreMask[i] |= ProcessorMask;
|
||||
break;
|
||||
}
|
||||
|
||||
} // for i
|
||||
|
||||
if (i == TotAvailCore) // did not match any bucket. Start a new one.
|
||||
{
|
||||
CoreIDBucket[i] = tblPkgID[ProcessorNum] | tblCoreID[ProcessorNum];
|
||||
pCoreMask[i] = ProcessorMask;
|
||||
|
||||
TotAvailCore++; // Number of available cores in the system
|
||||
|
||||
}
|
||||
|
||||
} // for ProcessorNum
|
||||
|
||||
|
||||
//
|
||||
// Count physical processor (PhysicalNum) in the system
|
||||
//
|
||||
U8 PackageIDBucket[256];
|
||||
DWORD pPackageMask[256];
|
||||
|
||||
PackageIDBucket[0] = tblPkgID[0];
|
||||
ProcessorMask = 1;
|
||||
pPackageMask[0] = ProcessorMask;
|
||||
|
||||
for (ProcessorNum = 1; ProcessorNum < numLPEnabled; ProcessorNum++)
|
||||
{
|
||||
ProcessorMask <<= 1;
|
||||
for (i = 0; i < PhysicalNum; i++)
|
||||
{
|
||||
// Comparing bit-fields of logical processors residing in different packages
|
||||
// Assuming the bit-masks are the same on all processors in the system.
|
||||
if (tblPkgID[ProcessorNum]== PackageIDBucket[i])
|
||||
{
|
||||
pPackageMask[i] |= ProcessorMask;
|
||||
break;
|
||||
}
|
||||
|
||||
} // for i
|
||||
|
||||
if (i == PhysicalNum) // did not match any bucket. Start a new one.
|
||||
{
|
||||
PackageIDBucket[i] = tblPkgID[ProcessorNum];
|
||||
pPackageMask[i] = ProcessorMask;
|
||||
|
||||
PhysicalNum++; // Total number of physical processors in the system
|
||||
|
||||
}
|
||||
|
||||
} // for ProcessorNum
|
||||
#endif
|
||||
|
||||
//
|
||||
// Check to see if the system is multi-core
|
||||
// Check if the system is hyper-threading
|
||||
//
|
||||
if (TotAvailCore > PhysicalNum)
|
||||
{
|
||||
// Multi-core
|
||||
if (MaxLPPerCore == 1)
|
||||
StatusFlag = CONFIG_MultiCoreAndHTNotCapable;
|
||||
else if (numLPEnabled > TotAvailCore)
|
||||
StatusFlag = CONFIG_MultiCoreAndHTEnabled;
|
||||
else StatusFlag = CONFIG_MultiCoreAndHTDisabled;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
// Single-core
|
||||
if (MaxLPPerCore == 1)
|
||||
StatusFlag = CONFIG_SingleCoreAndHTNotCapable;
|
||||
else if (numLPEnabled > TotAvailCore)
|
||||
StatusFlag = CONFIG_SingleCoreHTEnabled;
|
||||
else StatusFlag = CONFIG_SingleCoreHTDisabled;
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
return StatusFlag;
|
||||
}
|
||||
|
||||
} // namespace CPUInfo
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -29,13 +29,10 @@ namespace CPUInfo
|
|||
{
|
||||
enum EConfig
|
||||
{
|
||||
CONFIG_UserConfigIssue,
|
||||
CONFIG_SingleCoreHTEnabled,
|
||||
CONFIG_SingleCoreHTDisabled,
|
||||
CONFIG_SingleCoreAndHTNotCapable,
|
||||
CONFIG_MultiCoreAndHTNotCapable,
|
||||
CONFIG_MultiCoreAndHTEnabled,
|
||||
CONFIG_MultiCoreAndHTDisabled,
|
||||
};
|
||||
|
||||
inline bool isMultiCore( EConfig config )
|
||||
|
|
@ -44,7 +41,6 @@ namespace CPUInfo
|
|||
{
|
||||
case CONFIG_MultiCoreAndHTNotCapable:
|
||||
case CONFIG_MultiCoreAndHTEnabled:
|
||||
case CONFIG_MultiCoreAndHTDisabled:
|
||||
return true;
|
||||
|
||||
default:
|
||||
|
|
@ -65,11 +61,10 @@ namespace CPUInfo
|
|||
}
|
||||
}
|
||||
|
||||
EConfig CPUCount( U32& totalAvailableLogical,
|
||||
U32& totalAvailableCores,
|
||||
U32& numPhysical );
|
||||
|
||||
EConfig CPUCount( U32& totalAvailableLogical, U32& totalAvailableCores );
|
||||
} // namespace CPUInfo
|
||||
|
||||
void SetProcessorInfo(Platform::SystemInfo_struct::Processor& pInfo, const char* vendor, const char* brand);
|
||||
|
||||
#endif // _TORQUE_PLATFORM_PLATFORMCOUNT_H_
|
||||
|
||||
|
|
|
|||
|
|
@ -1,128 +0,0 @@
|
|||
;-----------------------------------------------------------------------------
|
||||
; Copyright (c) 2012 GarageGames, LLC
|
||||
;
|
||||
; Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
; of this software and associated documentation files (the "Software"), to
|
||||
; deal in the Software without restriction, including without limitation the
|
||||
; rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
; sell copies of the Software, and to permit persons to whom the Software is
|
||||
; furnished to do so, subject to the following conditions:
|
||||
;
|
||||
; The above copyright notice and this permission notice shall be included in
|
||||
; all copies or substantial portions of the Software.
|
||||
;
|
||||
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
; FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
; IN THE SOFTWARE.
|
||||
;-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
segment .text
|
||||
|
||||
; syntax: export_fn <function name>
|
||||
%macro export_fn 1
|
||||
%ifidn __OUTPUT_FORMAT__, elf
|
||||
; No underscore needed for ELF object files
|
||||
global %1
|
||||
%1:
|
||||
%else
|
||||
global _%1
|
||||
_%1:
|
||||
%endif
|
||||
%endmacro
|
||||
|
||||
; push registers
|
||||
%macro pushreg 0
|
||||
; pushad
|
||||
push ebx
|
||||
push ebp
|
||||
push esi
|
||||
push edi
|
||||
%endmacro
|
||||
|
||||
; pop registers
|
||||
%macro popreg 0
|
||||
pop edi
|
||||
pop esi
|
||||
pop ebp
|
||||
pop ebx
|
||||
; popad
|
||||
%endmacro
|
||||
|
||||
; void detectX86CPUInfo(char *vendor, U32 *processor, U32 *properties);
|
||||
export_fn detectX86CPUInfo
|
||||
push ebp
|
||||
mov ebp, esp
|
||||
|
||||
pushreg
|
||||
|
||||
push edx
|
||||
push ecx
|
||||
pushfd
|
||||
pushfd ; save EFLAGS to stack
|
||||
pop eax ; move EFLAGS into EAX
|
||||
mov ebx, eax
|
||||
xor eax, 0x200000 ; flip bit 21
|
||||
push eax
|
||||
popfd ; restore EFLAGS
|
||||
pushfd
|
||||
pop eax
|
||||
cmp eax, ebx
|
||||
jz EXIT ; doesn't support CPUID instruction
|
||||
|
||||
;
|
||||
; get vendor information using CPUID eax == 0
|
||||
xor eax, eax
|
||||
cpuid
|
||||
|
||||
; store the vendor tag (12 bytes in ebx, edx, ecx) in the first parameter,
|
||||
; which should be a char[13]
|
||||
push eax ; save eax
|
||||
mov eax, [ebp+8] ; store the char* address in eax
|
||||
mov [eax], ebx ; move ebx into the first 4 bytes
|
||||
add eax, 4 ; advance the char* 4 bytes
|
||||
mov [eax], edx ; move edx into the next 4 bytes
|
||||
add eax, 4 ; advance the char* 4 bytes
|
||||
mov [eax], ecx ; move ecx into the last 4 bytes
|
||||
pop eax ; restore eax
|
||||
|
||||
; get generic extended CPUID info
|
||||
mov eax, 1
|
||||
cpuid ; eax=1, so cpuid queries feature information
|
||||
|
||||
and eax, 0x0fff3fff
|
||||
push ecx
|
||||
mov ecx, [ebp+12]
|
||||
mov [ecx], eax ; just store the model bits in processor param
|
||||
mov ecx, [ebp+16]
|
||||
mov [ecx], edx ; set properties param
|
||||
pop ecx
|
||||
|
||||
; want to check for 3DNow(tm).
|
||||
; need to see if extended cpuid functions present.
|
||||
mov eax, 0x80000000
|
||||
cpuid
|
||||
cmp eax, 0x80000000
|
||||
jbe MAYBE_3DLATER
|
||||
mov eax, 0x80000001
|
||||
cpuid
|
||||
; 3DNow if bit 31 set -> put bit in our properties
|
||||
and edx, 0x80000000
|
||||
push eax
|
||||
mov eax, [ebp+16]
|
||||
or [eax], edx
|
||||
pop eax
|
||||
MAYBE_3DLATER:
|
||||
EXIT:
|
||||
popfd
|
||||
pop ecx
|
||||
pop edx
|
||||
|
||||
popreg
|
||||
|
||||
pop ebp
|
||||
ret
|
||||
|
|
@ -322,10 +322,9 @@ ThreadPool::ThreadPool( const char* name, U32 numThreads )
|
|||
// Platform::SystemInfo will not yet have been initialized.
|
||||
|
||||
U32 numLogical = 0;
|
||||
U32 numPhysical = 0;
|
||||
U32 numCores = 0;
|
||||
|
||||
CPUInfo::CPUCount( numLogical, numCores, numPhysical );
|
||||
CPUInfo::CPUCount( numLogical, numCores );
|
||||
|
||||
const U32 baseCount = getMax( numLogical, numCores );
|
||||
mNumThreads = (baseCount > 0) ? baseCount : 2;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue